#source [find interface/jlink.cfg]
#source [find target/imx6.cfg]

# SRST connects to POR_B
reset_config trst_and_srst srst_pulls_trst

# No RTCK
adapter_khz 1000
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }

# Avoid using SRST to reset, use the watchdog instead
#$_TARGETNAME configure -event reset-assert "$_TARGETNAME mwh 0x20bc000 4"

# Can't get watchdog to reset correctly yet.. for now, just don't reset here.
# We already did a reset back in init_reset anyway.
$_TARGETNAME configure -event reset-assert {}

# This delay affects how soon after SRST we try to halt, so make it as
# small as possible. However, if it is too small we will fail the JTAG scan.
# Delay determined by experimentation
jtag_ntrst_delay 1000

gdb_port 3333
telnet_port 4444

proc wdog_reset {} {
	mwh phys 0x20bc000 4
}

proc ddr_init {} {
	halt
	dap apcsw 1

	set MX6_IOM_DRAM_DQM0	0x020e05ac
	set MX6_IOM_DRAM_DQM1	0x020e05b4
	set MX6_IOM_DRAM_DQM2	0x020e0528
	set MX6_IOM_DRAM_DQM3	0x020e0520
	set MX6_IOM_DRAM_DQM4	0x020e0514
	set MX6_IOM_DRAM_DQM5	0x020e0510
	set MX6_IOM_DRAM_DQM6	0x020e05bc
	set MX6_IOM_DRAM_DQM7	0x020e05c4

	set MX6_IOM_DRAM_CAS	0x020e056c
	set MX6_IOM_DRAM_RAS	0x020e0578
	set MX6_IOM_DRAM_RESET	0x020e057c
	set MX6_IOM_DRAM_SDCLK_0	0x020e0588
	set MX6_IOM_DRAM_SDCLK_1	0x020e0594
	set MX6_IOM_DRAM_SDBA2	0x020e058c
	set MX6_IOM_DRAM_SDCKE0	0x020e0590
	set MX6_IOM_DRAM_SDCKE1	0x020e0598
	set MX6_IOM_DRAM_SDODT0	0x020e059c
	set MX6_IOM_DRAM_SDODT1	0x020e05a0

	set MX6_IOM_DRAM_SDQS0	0x020e05a8
	set MX6_IOM_DRAM_SDQS1	0x020e05b0
	set MX6_IOM_DRAM_SDQS2	0x020e0524
	set MX6_IOM_DRAM_SDQS3	0x020e051c
	set MX6_IOM_DRAM_SDQS4	0x020e0518
	set MX6_IOM_DRAM_SDQS5	0x020e050c
	set MX6_IOM_DRAM_SDQS6	0x020e05b8
	set MX6_IOM_DRAM_SDQS7	0x020e05c0

	set MX6_IOM_GRP_B0DS	0x020e0784
	set MX6_IOM_GRP_B1DS	0x020e0788
	set MX6_IOM_GRP_B2DS	0x020e0794
	set MX6_IOM_GRP_B3DS	0x020e079c
	set MX6_IOM_GRP_B4DS	0x020e07a0
	set MX6_IOM_GRP_B5DS	0x020e07a4
	set MX6_IOM_GRP_B6DS	0x020e07a8
	set MX6_IOM_GRP_B7DS	0x020e0748
	set MX6_IOM_GRP_ADDDS	0x020e074c
	set MX6_IOM_DDRMODE_CTL	0x020e0750
	set MX6_IOM_GRP_DDRPKE	0x020e0758
	set MX6_IOM_GRP_DDRMODE	0x020e0774
	set MX6_IOM_GRP_CTLDS	0x020e078c
	set MX6_IOM_GRP_DDR_TYPE	0x020e0798

	set MX6_MMDC_P0_MDCTL	0x021b0000
	set MX6_MMDC_P0_MDPDC	0x021b0004
	set MX6_MMDC_P0_MDOTC	0x021b0008
	set MX6_MMDC_P0_MDCFG0	0x021b000c
	set MX6_MMDC_P0_MDCFG1	0x021b0010
	set MX6_MMDC_P0_MDCFG2	0x021b0014
	set MX6_MMDC_P0_MDMISC	0x021b0018
	set MX6_MMDC_P0_MDSCR	0x021b001c
	set MX6_MMDC_P0_MDREF	0x021b0020
	set MX6_MMDC_P0_MDRWD	0x021b002c
	set MX6_MMDC_P0_MDOR	0x021b0030
	set MX6_MMDC_P0_MDASP	0x021b0040
	set MX6_MMDC_P0_MAPSR	0x021b0404
	set MX6_MMDC_P0_MPZQHWCTRL	0x021b0800
	set MX6_MMDC_P0_MPWLDECTRL0	0x021b080c
	set MX6_MMDC_P0_MPWLDECTRL1	0x021b0810
	set MX6_MMDC_P0_MPODTCTRL	0x021b0818
	set MX6_MMDC_P0_MPRDDQBY0DL	0x021b081c
	set MX6_MMDC_P0_MPRDDQBY1DL	0x021b0820
	set MX6_MMDC_P0_MPRDDQBY2DL	0x021b0824
	set MX6_MMDC_P0_MPRDDQBY3DL	0x021b0828
	set MX6_MMDC_P0_MPDGCTRL0	0x021b083c
	set MX6_MMDC_P0_MPDGCTRL1	0x021b0840
	set MX6_MMDC_P0_MPRDDLCTL	0x021b0848
	set MX6_MMDC_P0_MPWRDLCTL	0x021b0850
	set MX6_MMDC_P0_MPMUR0	0x021b08b8

	set MX6_MMDC_P1_MDCTL	0x021b4000
	set MX6_MMDC_P1_MDPDC	0x021b4004
	set MX6_MMDC_P1_MDOTC	0x021b4008
	set MX6_MMDC_P1_MDCFG0	0x021b400c
	set MX6_MMDC_P1_MDCFG1	0x021b4010
	set MX6_MMDC_P1_MDCFG2	0x021b4014
	set MX6_MMDC_P1_MDMISC	0x021b4018
	set MX6_MMDC_P1_MDSCR	0x021b401c
	set MX6_MMDC_P1_MDREF	0x021b4020
	set MX6_MMDC_P1_MDRWD	0x021b402c
	set MX6_MMDC_P1_MDOR	0x021b4030
	set MX6_MMDC_P1_MDASP	0x021b4040
	set MX6_MMDC_P1_MAPSR	0x021b4404
	set MX6_MMDC_P1_MPZQHWCTRL	0x021b4800
	set MX6_MMDC_P1_MPWLDECTRL0	0x021b480c
	set MX6_MMDC_P1_MPWLDECTRL1	0x021b4810
	set MX6_MMDC_P1_MPODTCTRL	0x021b4818
	set MX6_MMDC_P1_MPRDDQBY0DL	0x021b481c
	set MX6_MMDC_P1_MPRDDQBY1DL	0x021b4820
	set MX6_MMDC_P1_MPRDDQBY2DL	0x021b4824
	set MX6_MMDC_P1_MPRDDQBY3DL	0x021b4828
	set MX6_MMDC_P1_MPDGCTRL0	0x021b483c
	set MX6_MMDC_P1_MPDGCTRL1	0x021b4840
	set MX6_MMDC_P1_MPRDDLCTL	0x021b4848
	set MX6_MMDC_P1_MPWRDLCTL	0x021b4850
	set MX6_MMDC_P1_MPMUR0	0x021b48b8

	set CCM_CCGR0		0x020C4068
	set CCM_CCGR1		0x020C406c
	set CCM_CCGR2		0x020C4070
	set CCM_CCGR3		0x020C4074
	set CCM_CCGR4		0x020C4078
	set CCM_CCGR5		0x020C407c
	set CCM_CCGR6		0x020C4080

	# ddr-setup.cfg
	mww phys $MX6_IOM_DRAM_SDQS0 0x00000030
	mww phys $MX6_IOM_DRAM_SDQS1 0x00000030
	mww phys $MX6_IOM_DRAM_SDQS2 0x00000030
	mww phys $MX6_IOM_DRAM_SDQS3 0x00000030
	mww phys $MX6_IOM_DRAM_SDQS4 0x00000030
	mww phys $MX6_IOM_DRAM_SDQS5 0x00000030
	mww phys $MX6_IOM_DRAM_SDQS6 0x00000030
	mww phys $MX6_IOM_DRAM_SDQS7 0x00000030

	mww phys $MX6_IOM_GRP_B0DS 0x00000030
	mww phys $MX6_IOM_GRP_B1DS 0x00000030
	mww phys $MX6_IOM_GRP_B2DS 0x00000030
	mww phys $MX6_IOM_GRP_B3DS 0x00000030
	mww phys $MX6_IOM_GRP_B4DS 0x00000030
	mww phys $MX6_IOM_GRP_B5DS 0x00000030
	mww phys $MX6_IOM_GRP_B6DS 0x00000030
	mww phys $MX6_IOM_GRP_B7DS 0x00000030
	mww phys $MX6_IOM_GRP_ADDDS 0x00000030
	# 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe
	mww phys $MX6_IOM_GRP_CTLDS 0x00000030

	mww phys $MX6_IOM_DRAM_DQM0 0x00020030
	mww phys $MX6_IOM_DRAM_DQM1 0x00020030
	mww phys $MX6_IOM_DRAM_DQM2 0x00020030
	mww phys $MX6_IOM_DRAM_DQM3 0x00020030
	mww phys $MX6_IOM_DRAM_DQM4 0x00020030
	mww phys $MX6_IOM_DRAM_DQM5 0x00020030
	mww phys $MX6_IOM_DRAM_DQM6 0x00020030
	mww phys $MX6_IOM_DRAM_DQM7 0x00020030

	mww phys $MX6_IOM_DRAM_CAS 0x00020030
	mww phys $MX6_IOM_DRAM_RAS 0x00020030
	mww phys $MX6_IOM_DRAM_SDCLK_0 0x00020030
	mww phys $MX6_IOM_DRAM_SDCLK_1 0x00020030

	mww phys $MX6_IOM_DRAM_RESET 0x000e0030
	mww phys $MX6_IOM_DRAM_SDCKE0 0x00003000
	mww phys $MX6_IOM_DRAM_SDCKE1 0x00003000

	mww phys $MX6_IOM_DRAM_SDODT0 0x00003030
	mww phys $MX6_IOM_DRAM_SDODT1 0x00003030

	# (differential input)
	mww phys $MX6_IOM_DDRMODE_CTL 0x00020000
	# (differential input)
	mww phys $MX6_IOM_GRP_DDRMODE 0x00020000
	# disable ddr pullups
	mww phys $MX6_IOM_GRP_DDRPKE 0x00000000
	mww phys $MX6_IOM_DRAM_SDBA2 0x00000000
	# 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe
	mww phys $MX6_IOM_GRP_DDR_TYPE 0x000C0000

	# Read data DQ Byte0-3 delay
	mww phys $MX6_MMDC_P0_MPRDDQBY0DL 0x33333333
	mww phys $MX6_MMDC_P0_MPRDDQBY1DL 0x33333333
	mww phys $MX6_MMDC_P0_MPRDDQBY2DL 0x33333333
	mww phys $MX6_MMDC_P0_MPRDDQBY3DL 0x33333333
	mww phys $MX6_MMDC_P1_MPRDDQBY0DL 0x33333333
	mww phys $MX6_MMDC_P1_MPRDDQBY1DL 0x33333333
	mww phys $MX6_MMDC_P1_MPRDDQBY2DL 0x33333333
	mww phys $MX6_MMDC_P1_MPRDDQBY3DL 0x33333333

	# MDMISC	mirroring	interleaved (row/bank/col)
	mww phys $MX6_MMDC_P0_MDMISC 0x00081740

	# MDSCR	con_req
	mww phys $MX6_MMDC_P0_MDSCR 0x00008000



	# 1066mhz_4x128mx16.cfg
	mww phys $MX6_MMDC_P0_MDPDC 0x00020036
	mww phys $MX6_MMDC_P0_MDCFG0 0x555A7974
	mww phys $MX6_MMDC_P0_MDCFG1 0xDB538F64
	mww phys $MX6_MMDC_P0_MDCFG2 0x01FF00DB
	mww phys $MX6_MMDC_P0_MDRWD 0x000026D2
	mww phys $MX6_MMDC_P0_MDOR 0x005A1023
	mww phys $MX6_MMDC_P0_MDOTC 0x09444040
	mww phys $MX6_MMDC_P0_MDPDC 0x00025576
	mww phys $MX6_MMDC_P0_MDASP 0x00000027
	mww phys $MX6_MMDC_P0_MDCTL 0x831A0000
	mww phys $MX6_MMDC_P0_MDSCR 0x04088032
	mww phys $MX6_MMDC_P0_MDSCR 0x00008033
	mww phys $MX6_MMDC_P0_MDSCR 0x00428031
	mww phys $MX6_MMDC_P0_MDSCR 0x19308030
	mww phys $MX6_MMDC_P0_MDSCR 0x04008040
	mww phys $MX6_MMDC_P0_MPZQHWCTRL 0xA1390003
	mww phys $MX6_MMDC_P1_MPZQHWCTRL 0xA1390003
	mww phys $MX6_MMDC_P0_MDREF 0x00005800
	mww phys $MX6_MMDC_P0_MPODTCTRL 0x00022227
	mww phys $MX6_MMDC_P1_MPODTCTRL 0x00022227
	mww phys $MX6_MMDC_P0_MPDGCTRL0 0x42720306
	mww phys $MX6_MMDC_P0_MPDGCTRL1 0x026F0266
	mww phys $MX6_MMDC_P1_MPDGCTRL0 0x4273030A
	mww phys $MX6_MMDC_P1_MPDGCTRL1 0x02740240
	mww phys $MX6_MMDC_P0_MPRDDLCTL 0x45393B3E
	mww phys $MX6_MMDC_P1_MPRDDLCTL 0x403A3747
	mww phys $MX6_MMDC_P0_MPWRDLCTL 0x40434541
	mww phys $MX6_MMDC_P1_MPWRDLCTL 0x473E4A3B
	mww phys $MX6_MMDC_P0_MPWLDECTRL0 0x0011000E
	mww phys $MX6_MMDC_P0_MPWLDECTRL1 0x000E001B
	mww phys $MX6_MMDC_P1_MPWLDECTRL0 0x00190015
	mww phys $MX6_MMDC_P1_MPWLDECTRL1 0x00070018
	mww phys $MX6_MMDC_P0_MPMUR0 0x00000800
	mww phys $MX6_MMDC_P1_MPMUR0 0x00000800
	mww phys $MX6_MMDC_P0_MDSCR 0x00000000
	mww phys $MX6_MMDC_P0_MAPSR 0x00011006
	

	# clocks.cfg
	mww phys $CCM_CCGR0 0x00C03F3F
	mww phys $CCM_CCGR1 0x0030FC03
	mww phys $CCM_CCGR2 0x0FFFC000
	mww phys $CCM_CCGR3 0x3FF00000
	mww phys $CCM_CCGR4 0x00FFF300
	mww phys $CCM_CCGR5 0x0F0000C3
	mww phys $CCM_CCGR6 0x000003FF
}